This page collects all resources relevant to the FreePDK15TM 15nm variant of the FreePDKTM process design kit. This kit was developed in collaboration with MentorGraphics.
FreePDK15 code files have been open sourced under the New BSD Licence. The Free PDK Design Rule Kit is licensed under Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License (CC BY-NC-SA 4.0). By downloading or using this kit, (1) you accept the terms and conditions of the aforementioned licenses and (2) acknowledge that commercial use could require a commercial license. For a commercial license, please contact NCSU Technology Transfer at email@example.com.
- November 21, 2014 – Downloads of the FreePDK15 have been re-enabled with slight modification to the license terms. Academic users should see the license file in the new distribution. Commercial users should contact NCSU Technology Transfer at the address listed above.
- September 29, 2014 – Downloads of the FreePDK15 have been disabled since August 27 as NCSU reviews the license terms for the kit. Once an agreement is reached regarding the license, we will re-enable downloads and post announcements on this page and to our announcements mailing list. The new license will still be free for universities. The kit will unfortunately no longer be free for commercial users, but will be available to commercial users for a small fee. Please contact us at firstname.lastname@example.org for more information about commercial use licenses.
- July 22, 2014 – The initial release of the FreePDK15 is now available. This version of the kit includes the technology library for Cadence Virtuoso and Synopsys PyCell and design rules for Mentor Graphics Calibre. Please see the release notes below for details on what’s included in this release and what we have planned for the next release.
- May 29, 2014 – Come see us at the DAC! We will present a Demo of the FreePDK15 at the SIGDA University Booth at 3:15-4:45pm on both Monday, June 2 and Wednesday, June 4. See also the demo of the Nangate Open Cell Library based on this kit. Note that as of today, the name of the kit is changing from FreePDK14 to FreePDK15, in order to maintain consistency with the NanGate Open Cell Library release. The DAC Demo may still reference the old name.
- Current Design Rules
- Design Rule Manual – This link directs you to Kirti Bhanushali’s thesis. Chapter 4 of this document provides the best introduction to the rules that we currently have available. Please check the Current Design Rules link above for the latest rules, as they have changed slightly since publication of the thesis.
Release Notes for FreePDK15 1.1 (2014-11-21) (Git Repository Commit 2014-11-21)
Changes in this release
- Slight changes to license agreement and inclusion of license statement in every file. No other changes.
Release Notes for FreePDK15 1.0 (2014-07-22) (Git Repository Commit 2014-07-22)
Included in this release
- Technology library and display resources for Cadence Virtuoso (Tested with Virtuoso 6.1.5 01/16/2012)
- Calibre DRC rules (Tested with Calibre 2011.3_18.12)
- P-Cells for the CiraNova/Synopsys PyCell (Tested with PyCell 4.2.5-L2 Jun 27 2008)
Planned for the next release
- HSPICE models
- Calibre LVS and xRC rules
Issues with this release
- P-Cells are not ready for use. One reason for the delay is that we have not successfully compiled the technology library with Synopsys PyCell 2013.12. We are not currently working on this issue due to lack of resources and are instead focusing on LVS/xRC rules. The P-Cells included with this kit are intended rather to illustrate the current status of the code and provide a starting point for someone to begin debugging.
- Design rules are subject to change. We are iterating with NanGate and Mentor Graphics on design rules and anticipate another release later this year. A summary of the issues we are currently considering can found by running DRC on the SDFFRNQ_X1 cell from the NanGate 15nm Open Cell Library:
Rule Name Description Result Count --------- --------------------------------------------- ------------ ACT.5 Horizontal Spacing of ACT 2 AIL2.3 Minimum spacing between AIL2 and GATE[A|B] 2 AIL2.5 Minimum vertical overlap of AIL1 and AIL2 15 AIL2.10 Vertical spacing of AIL2 and AIL1 on different net 9 GIL.8 Minumum vertical spacing of GIL to AIL2 4 V0.9 Minimum space of V0 and GIL on different net 17 M1.3 Maximum length of M1[A|B] for wires w/ min width 28nm 2 M1.8,9 Minumum spacing of M1[A|B] 5 M1.15,16 M1[A|B] minimum spacing to M1[B|A] 16 MINT.3 Maximum length of MINTn[A|B] for wires w/ min width 28nm 2
Some of these violations may be fixed through further clarification of each rule and modification of the calibre rules. Others may result in small chances to rule values.