NC State University Cadence Design Kit

NC State University’s Cadence environment has been customized with several technology files and a fair amount of custom SKILL code. These files contain information useful for analog/full-custom digital CMOS IC design via the MOSIS IC fabrication service. This information includes layer definitions (e.g. colors, patterns, etc.), parasitic capacitances, layout pcells, SPICE simulation parameters, Diva rules for DRC, extraction, and LVS verification, and various GUI enhancements. This environment is available as the NCSU Cadence Design Kit (NCSU CDK).

The NCSU CDK can be used with at least versions 4.4 through 5.1 of the Cadence software toolset and is available free of charge as a service to the Cadence design community.

The original NCSU CDK was authored by Toby Schaffer, Alan Glaser, and Andy Stanaski in 1996. Their good work has been sustained and supported by many others since then.

Support for this effort comes from DARPA, NSF, SRC, and the NCSU Analog Alliance. The effort is directed by Professor Paul Franzon and Professor Rhett Davis.

Current Versions

(PLEASE NOTE: You can subscribe to our extremely low-traffic announcements mailing list to receive email alerts when we update our kits.)

  • The most current supported version of the NCSU CDK is 1.5.1, for use with Cadence Virtuoso versions 5.1.41 and earlier.

In addition, a beta test version of NCSU CDK is available (1.6.0.beta), for use with OpenAccess, Cadence Virtuoso versions 5.2.51, 6.1, and later. 


The NCSU CDK focuses on providing the means to do full-custom CMOS IC design (SCMOS design rules) through MOSIS, including schematic entry, Verilog digital simulation, analog circuit simulation, layout DRC checking and device extraction, and mask generation. It requires Cadence 4.4 or higher and is not backward compatible with 4.3.x. All SKILL code is available as source.

The tools used in the kit are Virtuoso, Composer, Analog Artist, Virtuoso-XL and Diva.

What it is…

In particular, the kit features:

  • support for all MOSIS processes which support the SCMOS rules, including process-dependent layers, e.g., pbase for NPNs
  • layermaps for MOSIS CIF/GDSII import/export
  • Diva verification: DRC (all rules from the MOSIS SCMOS User’s Manual 8.0 excluding some DEEP rules and wide-metal spacing rules), extraction (MOSFETs, high-voltage MOSFETs, cwell/{m1,elec,polycap}-poly/inter-metal/metalcap/parasitic capacitors, vertical NPN BJTs, diodes, resistors), and LVS
  • Composer with interface to:
    • HSPICE/Spectre through Analog Artist, with MOSIS-provided transistor models in place
    • Verilog with technology-independent parts
  • technology-independent libraries for analog (eg, RLC, transistors) and digital (eg, gates) parts. These parts have SKILL code hooked in to enforce sizing and grid rules (eg, minimum width/length, half-lambda grid), automatic transistor model selection depending on technology, and drain/source area/perimeter estimation.
  • technology libraries (ie, one library for every MOSIS SCMOS process) with parameterized layout cells setup for both manual use and layout synthesis via Virtuoso-XL
  • MOSIS wirebond pads (HP 0.6um; AMI 0.6um; TSMC 0.40um)
  • various user-friendly GUI enhancements
  • documentation of all customizations in HTML

and what it isn’t…

A few big things that the kit does not expressly do:

  • Place and Route
  • provide a standard cell layout library
  • digital timing analysis
  • parasitic resistance extraction