This page collects all resources relevant to the FreePDK3D45TM 3D-IC variant of the FreePDKTM process design kit.

News

  • July 28, 2011 – Version 1.1 of the FreePDK3D45 has been released, featuring a 5-tier technology, new design rules, and instructions for compiling variants of this kit. Many of the improvements from the FreePDK45 1.4 have also been included. See the release notes below for more details.
  • June 5, 2009 – Version 1.0 of the FreePDK3D45 has been released. This kit is a 3D-IC Version of the FreePDK. The current kit is for a two-tier, face-to-face, bulk process, however the kit is capable of producing a three-tier version with some modification. Please contact us for more details on generating variants of this kit. The pages linked here are our primary documentation for the kit and show our current status.

Current Version

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Release Notes

The following is pasted from the $PDK_DIR/ncsu_basekit/doc/FreePDK3D45_Release_Notes.txt file, included in the distribution:

==================================================================
 Contents: Release Notes for the 3D version of the FreePDK45
 File: FreePDK3D45_Release_Notes.txt
 Created: July 27, 2011
==================================================================

Release Notes for FreePDK3D45 1.1 (2011-07-28) 

New in this release:
 - Support for 5-tier, 45nm bulk CMOS stacks
 - Notes for compiling variants of the kit
 - Calibre DRC rules for TSV density
 - HSPICE models and Schematic Entry updates 
     to match FreePDK45 1.4 (2011-04-07)

Design Rule Differences with FreePDK45 1.4:
 - Calibre DRC Antenna rules not included
 

Release Notes for FreePDK3D45 1.0 (2009-6-5)

Included in this release:
 - Support for 2-tier, 45nm bulk CMOS stacks
 - Technology library and display resources for Cadence Virtuoso
 - Calibre DRC & LVS rules
 - Support for CiraNova PyCell plugin (No P-Cells included)
 - Support for schematic simulation with HSPICE
 - Example layout and schematic
 - Based on FreePDK45 1.3 (2009-03-04)

User Guide

Manual

The following is pasted from the $PDK_DIR/ncsu_basekit/doc/FreePDK3D45_Manual.txt file, included in the distribution:

=============================================================================
 Contents: Manual for the 3D version of the FreePDK45
 File: FreePDK3D45_Manual.txt
 Created: June 4, 2009
=============================================================================

 Update History:
    Date        who                       Update Details:
-----------------------------------------------------------------------------
 2009-06-04    slipa/wdavis  First version, modified from the 3D_PDK3.0 
                             for the MITLL 3D technology.
 2011-07-28    wdavis        Updated for release 1.1 of the kit
-----------------------------------------------------------------------------

***** Please send all questions and comments to eda_help@ncsu.edu! *****

Contents:

I.      Introduction
II.     Layer Cross-Reference
III.    Through-Silicon Vias
IV.     Parameterized Cells
V.      Example Layout
VI.     Display Options and Other Menu Options
VII.    Compiling Variants of this Kit

--------------------------------------------------------------------------
I.    Introduction
--------------------------------------------------------------------------

The FreePDK3D45 is a free, open source design kit compiler for stacked
dies (i.e. 3D-ICs) in a predictive 45nm technology, made possible
through the support of the Semiconductor Research Corporation.  The
kit as downloaded represents a five-tier stack of the FreePDK45
predictive technology and includes the files needed to compile other
stacks.

Unlike the FreePDK45, which is intended for VLSI education, this kit
is intended for use in demonstrating and debugging new
OpenAccess-based design tools for 3D-ICs.  As such, this kit contains
the basics of what is needed to perform schematic entry, SPICE
simulation, layout, DRC, and LVS checks.  Many of the features of the
single-tier FreePDK45 are not included with this kit, such as
parasitic extraction, lithography simulation, and some of the more
complex design rules (like Antenna rules).

This document contains notes on the particulars of how 3D stacked
versions of the FreePDK45 were created.  It it not intended to be a
complete manual for the PDK, but rather a list of caveats that must be
considered when applying the FreePDK45 design flows to 3D chip stacks.

The design flow assumes the stackup included in the file
$PDK_DIR/ncsu_basekit/doc/Stackup.png, which is described in more
detail at http://www.eda.ncsu.edu/wiki/FreePDK3D45:Metal_Layers.  
We assume that Tier 1(A) will be "face up" and Tiers 2(B) through 5(E)
will be "face down."

The technology file includes 5 simultaneous Tiers allowing the
designer to maintain a complete 3D conception of his design.  Tiers
1(A) through 5(E) are provided for implementation of a complete 3D
design.  The layer names associated with these Tiers use alphabetic
suffixes.  Thus, the third-layer metal on Tier 2(B) is metal3_B.

This manual and the FreePDK45_Manual.txt are intended as introductions
to the kit, but they are by no means comprehensive.  Please see the
FreePDK Wiki for complete documentation:

http://www.eda.ncsu.edu/wiki/FreePDK


--------------------------------------------------------------------------
II.   Layer Cross-Reference
--------------------------------------------------------------------------

Layers 1-34 in this kit are basically the same as with the FreePDK45.
These layers are assumed to be "tier non-specific", meaning that they
are not assumed to be on any tier.  These layers are not checked by
the Calibre DRC or LVS rules.  They are purely for convenience
when importing GDS, LEF, and DEF files.  The file 
$PDK_DIR/ncsu_basekit/techfile/techdefs.txt contains the complete
list of "tier non-specific" layers.  This file is used to compile the
technology files for Ciranova Pycell and Cadence Virtuoso.

The tier-specific layer numbers are determined by adding an offset for
that tier.  The tier-specific layer name can be determined by
appending a suffix for that tier.  The offsets and suffixes are given
below:

Tier Offset Suffix
---- ------ ------
1(A)  300    _A
2(B)  600    _B
3(C)  900    _C
4(D) 1200    _D
5(E) 1500    _E

For those unfamiliar with Ciranova Pycell techfiles, please see the 
layerMapping() section of the file 
$PDK_DIR/ncsu_basekit/techfile/cni/Santana.tech
for the complete list of layer names.


--------------------------------------------------------------------------
III.  Through-Silicon Vias
--------------------------------------------------------------------------

All vias in this kit are Open-Access standard-vias, with the execption of
a few custom vias, as described in FreePDK45_Manual.txt.  Most vias are 
self-explanatory, following the same naming scheme as with the FreePDK45, 
but with an _A or _B suffix to denote which tier they are on.  Vias without
a suffix are assumed to be tier-non-specific.

The vias that will need some explanation are the "Through-Silicon
Vias" (TSVs), also sometimes called "Through-Stack Vias".  The metal
cross section diagram in $PDK_DIR/ncsu_basekit/doc/Stackup.png and
http://www.eda.ncsu.edu/wiki/FreePDK3D45:Metal_Layers illustrates how
a TSV from tier A to tier B is created by assuming a "Top Metal" layer
(TM) for each tier and a via from M10 to the top-metal (using a
special "up" via cut-layer called VUP).  A connection is made by
bonding two top-metal shapes face-to face.

Similarly, a back-metal (BM) is assumed to be patterned on the back of
the substrate.  A special "down" via cut-layer (VDN) is used for
connection to the back-metal.  Although not illustrated in the figure,
a fact-to-back TSV would be implemented by bonding top-metal to back-metal.

In the event that a foundry wants to create a large via through the entire 
tier, a special "through-tier" via cut-layer (VTT) has been added.  This 
cut layer may not be necessary, but many researchers have proposed that
they can be useful for such tasks as heat-removal.

From a user perspective, the standard vias TM_M10 and M1_BM have been
created to allow connection to top-metal and back-metal on any tier.
Users can create TSVs by using the appropriate combination of
tier-specific standard vias.  For example, a connection from tier A to
tier B is accomplished with a combination of TM_M10_A and TM_M10_B.  A
connection off-chip is accomplished with M1_BM_B.  This approach is
somewhat confusing, but it allows this kit to compile other
tier-stacks with minimal effort.

Finally, special vias have been added to handle the VTT cuts.  These
vias are called TM_A_BM_B, BM_B_BM_C, BM_C_BM_D, and BM_D_BM_E.  These
vias are handled as a special case by our compiler.

--------------------------------------------------------------------------
IV.  Parameterized Cells
--------------------------------------------------------------------------

Although this kit was compiled with Ciranova Pycell and can support
Pycell P-Cells, P-cells are not included with this kit.  It is assumed
that this kit will be used to help debug new, 3D-IC-enabled,
OpenAccess-based tools, rather than to perfrom custom layout in 3D-IC
technologies.  We will investigate the possibility of including
P-cells as new tools become available.

--------------------------------------------------------------------------
V.   Example Layouts
--------------------------------------------------------------------------

The $PDK_DIR/examples directory contains an example library LVS_test 
with sample cells.

  LVS_test - Contains INVS_test, an example of an inverter chain 
               in five tiers.
  DRC_test - Contains two example layouts of designs that fail and
               pass the TSV density design rule.

Further example layout can be generated quickly by using the
standard-cells in the FreePDK45 or the Nangate Open Cell Library.
Both of these libraries are layer-compatible with this kit.  Layout
can be moved between tiers with the "Move figures between Tiers"
option in the 3DIC menu.

--------------------------------------------------------------------------
VI.  Display Options and Other Menu Options
--------------------------------------------------------------------------

This Kit offers the ability to change tier visibility, in order to
help visualize 3D Designs.  The is done with the following items from
the "3DIC" Menu in Virtuoso:

         View Tier A
         View Tier B
         View Tier C
         View Tier D
         View Tier E
         View All Tiers

These menu options allow the user to view only one tier at a time or
to see all tiers simultaneously.  For example, choosing "View Tier A"
will make all layers in tiers B through E invisible and non-selectable in
the Layer Selection Window (LSW).  Choosing "View All Tiers" returns
to the default.

These menu options basically load the LSW SKILL commands from the
files (named layerDisplay_#.il) in the ncsu_basekit/skill/display/
directory.  Modify these files if you want to set your own options.

In addition to these display options, a menu option called "Move figures
between Tiers" is available to help you to migrate a design done on one
Tier to another Tier.  Its use is self-explanatory.


--------------------------------------------------------------------------
VII.    Compiling Variants of this Kit
--------------------------------------------------------------------------

Because 3D-IC technologies are very diverse, it is likely that this
kit will need to be modified to represent the particulars of a desired
stacking technology.  The first step in such modification should be to
create a new graphic to illustrate the stack.  The file
$PDK_DIR/ncsu_basekit/doc/Stackup.vsd provides a Microsoft Visio file
that can be freely modified and distributed to describe new stacks.
For those without access to Microsoft Visio, a PNG image is also
provided.

The stackup graphic shows the additional "Stack Technology Layers"
that are added to the top and bottom of a traditional wafer technology
(such as the FreePDK45).  Each instance of a wafer technology and its
associated stacking layers above and below are considered to be a
"tier" by this kit.  This approach allows a reduction in the number of
required layer names.  Five new layer names are used, as described in
the "Through-Silicon Vias" section above.  It is assumed that most
users will want to modify the stack-technology layers and not the
wafer technology layers.

== Compiling The Technology Library ==

The technology library NCSU_TechLib_FreePDK3D45 must be re-compiled
for the following changes:
  - Adding or removing tiers
  - Adding or removing layers
  - Modifying the standard via definitions

If you need to make any of these changes, then note the following:
  - Refer to the following web-page for instructions on how to
    compile a new technology library for the single-tier FreePDK45:
    http://www.eda.ncsu.edu/wiki/FreePDK45:Developer_Getting_Started
  - This kit uses a similar "gentech.py" script to compile the 
    technology.  The primary difference is that another script is 
    called, which is defined in
    $PDK_DIR/ncsu_basekit/gentech/sshaft/src/py/gen3Dtech.py.
  - The gen3Dtech.py script generates both the Pycell "Santana.tech" 
    file and Virtuoso "FreePDK3D45.tf" files used by gentech.py.
  - The gen3Dtech.py script also generates the layerDisplay.il file,
    which is current modified by hand to produce the files in the
    $PDK_DIR/ncsu_basekit/skill/display directory, which enable
    selectively displaying tiers.

== Modifying the Techfiles ==

Modification of the tiers and layers can be accomplished by modifying
the gen3Dtech.py script until the desired kit is achieved.  We expect
that the existing layers and tiers are overkill for most applicatoins,
and so we will not go into greater detail on layer/tier modification
in this document.

Because the standard-via definitions are rather complex, the techfile
code for these vias is currently hand-authored and not generated by
the gen3Dtech.py script.  The file
$PDK_DIR/ncsu_basekit/techfile/cds_others_5.txt currently contains the
"viaDef" section of the Virtuoso technology file and is concatenated
into FreePDK3D45.tf.  We recommend modifying this file and
re-compiling with gentech.py to produce new via behavior.  Note that
the file "cds_others_2.txt" is the file we use to generate 2-tier
variants of this kit.

== Modifying the Calibre Rules ==

DRC and LVS rules are not modified by the gentech.py script described
above.  Rather, the DRC and LVS rules have been compiled with a script
developed by MIT Lincoln Laboratories.  This script can be found at
the following location:
$PDK_DIR/ncsu_basekit/techfile/calibre/convert_to_3d_rules.pl

Use this script to generate multi-tier versions of a single-tier
rule file with the following command:

./convert_to_3d_rules.pl -infile [rulefile] -config FreePDK3D45.cfg -outpath .

This approach is used on the following rule-files to produce the
indicated multi-tier rule-files in the same directory:
 - FreePDK45_master_top.rules  => 3D_FreePDK45_master_top.rules
 - FreePDK45_drc.rules         => 3D_FreePDK45_drc.rules
 - FreePDK45_lvs.rules         => 3D_FreePDK45_lvs.rules

The file 3D_FreePDK45_density.rules contains the TSV density rules, 
which have not yet been incorporated in the the perl-script.

Finally, the files 3D_FreePDK45_calibreDRC.rules and
3D_FreePDK45_calibreLVS.rules are the top-level files that
reference the four "3D_*" files mentioned above.

The most-likely change that we imagine users wanting to make will be
the LVS connections through the stack layers.  These connections are
defined with the SVRF "connect" commands located at the bottom of the
3D_FreePDK45_calibreLVS.rules file.  Note that modifying these
connections does not require re-generation of the multi-tier versions
of the wafer-technology rules.

Happy modifying!


***** Please send all questions and comments to eda_help@ncsu.edu! *****
Metal Layers

Five-Tier Bulk Option

Metal Layers

The material information in this table is for one tier. All tiers share the same parameters.

Dielectrics for VDN, VUP & VTT consist of other dielectric layers.

   VUP: TM Cap Oxide (1000 nm)
   VDN: from Poly-Dielectric to BM Cap Oxide (1570 nm)
   VTT: from TM to BM Cap Oxide (14090 nm)
Name Pitch (Width/Space) (nm) Thickness (nm) (1) Resistivity (ohm/sq) Permittivity Via dimension (nm) via resistance (ohm) (2)
Top Metal 1600 (800/800) 1000 (4) 0.060 (4) 2.5
TM Cap Oxide 1000 2.5 800 0.25
ILD 9 2000 2.5 800 0.5
Global(9-10) 1600 (800/800) 2000 0.030 (3) 2.5
ILD 7-8 820 2.5 400 1
ThinGlobal (7-8) 800 (400/400) 800 0.075 (3) 2.5
ILD 4-6 290 2.5 140 3
Semi-global 280 (140/140) 280 0.21 2.5
ILD 2-3 120 2.5 70 5
Intermediate (2-3) 140 (70/70) 140 0.25 2.5
ILD 1 120 2.5 65 6
Metal 1 130 (65/65) 130 0.38 2.5
Poly-Dielectric 85 2.5 65 8
Poly 125 (50/75) 85 7.8 2.5
Gate Oxide 200 2.5 6000 (5) 0.2 (5)
Substrate 40000 2.5 6000 (5) 0.2 (5)
BM Cap Oxide 200 2.5 6000 (5) 0.2 (5)
Back Metal 1600 (800/800) 1000 (4) 0.060 (4) 2.5

Metal Cross-Section Diagram

The image below illustrates the tier and metal stack-up of the 5-tier bulk version of this kit. Note that the thicknesses are not to scale!

FreePDK3D45 5TierBulk Stackup.png

Notes

(1) Thickness calculated from (Pitch/2) * Aspect Ratio, modified with data from reference 2.
(2) In [7], CVD tungsten is assumed to have a resistivity of 20 uOhm-cm (200 Ohm-nm). The contact and via resistances are calculated from the length and width values of each via, assuming this resistivity.
(3) Sheet resistances for global and thin-global metal are extrapolated from the value for semi-global metal, assuming the same material and an increase in thickness.
(4) It’s an estimated value for TM & BM thickness.
(5) The Via dimension listed here is for VDN on top tier. The Via resistance is for a whole VDN.

References

[1] The International Technology Roadmap for Semiconductors (ITRS): Executive Summary, 2005 Edition, p. 5., available online at http://www.itrs.net
[2] V. Arnal et. al., “45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5,” Proc. of the IEEE International Interconnect Technology Conference (IITC), pp. 213-215, June 5-7 2006.
[3] V. Nguyen et. al., “An AnaIysis of the Effect of Wire Resistance on Circuit Level Performance at the 45-nm Technology Node,” Proc. of the IEEE International Interconnect Technology Conference (IITC), pp. 191-193, June 6-8 2005.
[4] S. Narasimha et. al., “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[5] H. Nii et. al., “A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[6] N. Oda et. al., “Chip Level Performance Maximization Using ASIS (Application Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Devices”, IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 5-7 2005.
[7] I. Shao et. al., “An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond”, IEEE International Interconnect Technology Conference, pp. 102-104, Jun. 4-6 2007.

Developer Guide

Design Rules Development

This page is the updating rules for NCSU 45nm 3DPDK. It’s created based on rules of 2D FreePDK45.

The rules are listed in the order that decisions were made, along with a brief rule description and one or more notes giving a rationale. When possible, key-words in the rule description are linked to a set of standard Verification Rule Types. Names of Metal layers and 3D Vias (VUP, VDN & VTT) are re-directed to the new created 3D_FreePDK45 page, and other layers are still linked to FreePDK45.

For each tier, the verification rules names are consisted of “TIER#_” and names listed in the table below. Extra rules for 3D layers are listed at the end of the table.

Rule Value Description Notes
WELL.1 none saveDerived: nwell/pwell must not overlap (10)
WELL.2 225 nm Minimum spacing of nwell/pwell at different potential (10) (11)
WELL.3 135 nm Minimum spacing of nwell/pwell at the same potential (10) (11)
WELL.4 200 nm Minimum width of nwell/pwell (10) (11)
VT.1 none Vt adjust layers must coincide with well
POLY.1 50 nm Minimum width of poly (1)
POLY.2 140 nm Minimum spacing of poly AND active (2)
POLY.3 55 nm Minimum poly extension beyond active (3)
POLY.4 70 nm Minimum enclosure of active around gate (10) (11)
POLY.5 50 nm Minimum spacing of field poly to active (10) (11)
POLY.6 75 nm Minimum Minimum spacing of field poly (14)
ACTIVE.1 90 nm Minimum width of active (4)
ACTIVE.2 80 nm Minimum spacing of active (4)
ACTIVE.3 55 nm Minimum enclosure/spacing of nwell/pwell to active (5)
ACTIVE.4 none saveDerived: active must be inside nwell or pwell (8)
IMPLANT.1 70 nm Minimum spacing of nimplant/ pimplant to channel (10) (11)
IMPLANT.2 25 nm Minimum spacing of nimplant/ pimplant to contact (10) (11)
IMPLANT.3/4 45 nm Minimum width/ spacing of nimplant/ pimplant (10) (11)
IMPLANT.5 none Nimplant and pimplant must not overlap
CONTACT.1 65 nm Minimum width of contact (6)
CONTACT.2 75 nm Minimum spacing of contact (6)
CONTACT.3 none saveDerived: contact must be inside active or poly or metal1 (8)
CONTACT.4 5 nm Minimum enclosure of active around contact (8) (12)
CONTACT.5 5 nm Minimum enclosure of poly around contact (8) (12)
CONTACT.6 35 nm Minimum spacing of contact and poly (10) (12)
METAL1.1 65 nm Minimum width of metal1 (7)
METAL1.2 65 nm Minimum spacing of metal1 (7)
METAL1.3 35 nm Minimum enclosure around contact on two opposite sides (13)
METAL1.4 35 nm Minimum enclosure around via1 on two opposite sides (13)
METAL1.5 90 nm Minimum spacing of metal wider than 90 nm and longer than 900 nm (16)
METAL1.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALl1.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALl1.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METAL1.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA1.1 65 nm Minimum width of via1 (8) (9) 15
VIA1.2 75 nm Minimum spacing of via1 (8) 15
VIA1.3 none saveDerived: via1 must be inside metal1 (8)
VIA1.4 none saveDerived: via1 must be inside metal2 (8)
METALINT.1 70 nm Minimum width of intermediate metal (7)
METALINT.2 70 nm Minimum spacing of intermediate metal (7)
METALINT.3 35 nm Minimum enclosure around via1 on two opposite sides (13)
METALINT.4 35 nm Minimum enclosure around via[2-3] on two opposite sides (13)
METALINT.5 90 nm Minimum spacing of metal wider than 90 nm and longer than 900 nm (16)
METALINT.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALINT.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALINT.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALINT.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[2-3].1 70 nm Minimum width of via2 (15)
VIA[2-3].2 85 nm Minimum spacing of via2 (15)
VIA[2-3].3 none saveDerived: via2 must be inside metal2 (8)
VIA[2-3].4 none saveDerived: via2 must be inside metal3 (8)
METALSMG.1 140 nm Minimum width of semi-global metal (7)
METALSMG.2 140 nm Minimum spacing of semi-global metal (7)
METALSMG.3 0 nm Minimum enclosure around via[3-6] on two opposite sides (13)
METALSMG.6 270 nm Minimum spacing of metal wider than 270 nm and longer than 300 nm (16)
METALSMG.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALSMG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
VIA[4-6].1 140 nm Minimum width of via4 (15)
VIA[4-6].2 160nm Minimum spacing of via4 (15)
VIA[4-6].3 none saveDerived: via4 must be inside metal4 (8)
VIA[4-6].4 none saveDerived: via4 must be inside metal5 (8)
METALTNG.1 400 nm Minimum width of thin global metal (7)
METALTNG.2 400 nm Minimum spacing of thin global metal (7)
METALTNG.3 0 nm Minimum enclosure around via[6-8] on two opposite sides (13)
METALTNG.7 500 nm Minimum spacing of metal wider than 500 nm and longer than 1.8um (16)
METALTNG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALTNG.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[7-8].1 400 nm Minimum width of via[7-8] (15)
VIA[7-8].2 440 nm Minimum spacing of via[7-8] (15)
VIA[7-8].3 none saveDerived: via[7-8] must be inside metal[7-8] (8)
VIA[7-8].4 none saveDerived: via[7-8] must be inside metal[8-9] (8)
METALG.1 800 nm Minimum width of global metal (7)
METALG.2 800 nm Minimum spacing of global metal (7)
METALG.3 0 nm Minimum enclosure around via[8-9] on two opposite sides (13)
METALG.8 900 nm Minimum spacing of metal wider than 900 nm and longer than 2.7 um (16)
METALG.9 1500 nm Minimum spacing of metal wider than 1500 nm and longer than 4.0 um (16)
VIA[9].1 800 nm Minimum width of via9 (15)
VIA[9].2 880 nm Minimum spacing of via9 (15)
VIA[9].3 none saveDerived: via9 must be inside metal9 (8)
VIA[9].4 none saveDerived: via9 must be inside metal10 (8)
VUP.1 800 nm Minimum width of VUP
VUP.2 880 nm Minimum spacing of VUP
VUP.3 none saveDerived: VUP must be inside metal10
VUP.4 none saveDerived: VUP must be inside Top Metal
TM.1 800 nm Minimum width of Top Metal
TM.2 800 nm Minimum spacing of Top Metal
TM.3 600 nm Minimum enclosure around VUP on two opposite sides
VDN.1 6000 nm Minimum width of VDN (17)
VDN.2 6000 nm Minimum spacing of VDN (17)
VDN.3 none saveDerived: VDN must be inside metal1 (17)
VDN.4 none saveDerived: VDN must be inside Back Metal (17)
VDN.[5-6] 120nm Minimum spacing of VDN to active & poly
BM.1 800 nm Minimum width of Back Metal (17)
BM.2 800 nm Minimum spacing of Back Metal (17)
BM.3 600 nm Minimum enclosure around VDN on two opposite sides (17)
VTT.1 6000 nm Minimum width of VTT
VTT.2 6000 nm Minimum spacing of VTT
VTT.3 6000 nm Minimum spacing of VTT to VDN
VTT.[4-16] 250nm Minimum spacing of VTT to active, poly, metal[1-10] & Top Metal
GRID.[1-26] 2.5 nm Shapes on all layers must be on a 2.5 nm grid

Notes

(1) 50nm was chosen for the minimum width rectangle for poly, becasuse it is easier to design with than 45nm. It is assumed that the actual gate length is 45nm. In addition, the electron-micrograph in Fig. 18 in [3] appears to be about 50nm.
(2) Poly gate spacing is listed as 140 nm in Table 1 of [3]. Examining the electron-micrographs in other papers, the spacing appears to be 75nm in [2] and 125nm in [1]. In order to be a conservative set of rules, we should probably set the rule to be the largest of the three (namely, 140nm).
(3) Minimum poly extension beyond active varies from paper to paper, but appears to be on the order of the width of the poly line in most cases. Increased to 55 nm for manuracturablitiy based on advice from  ?????
(4) Table 1 in [1] and Table 1 in [3] both list minimum active width of 60 nm and spacing of 80 nm. However, Anupama Subramaniam of Marvell suggests that active width should be at least twice the gate length for better yield (giving 90nm).
(5) Min. spacing of N+ and P+ is listed as 102 nm in Table 1 of [2]. By setting the well/active enclosure/spacing to 55 nm, we effectively make this space 110 nm, which is slightly conservative and aligned to our 5 nm manufacturing grid.
(6) Contact width/space is given as 66/74 in Table 1 of [1] and 60/80 in Table 1 of [3] (giving a pitch of 140 nm in both cases). We chose 65/75 because it is in the middle and aligned to the 5nm grid, while still offering a pitch of 140 nm.
(7) Metal rules taken from the half/pitch values in table 1 of [2], which are nearly identical to the values in table 1 of [1] and table 4 of [3]. The only differences are that the width/space of metal1 are listed as 60/70 in [3] (still a pitch of 130 nm), and the global wiring has a pitch of 2000 nm in [1].
(8) Rules are taken from an example Diva DRC file in the Diva reference.
(9) Value taken from FreePDK45.tf, in which values were scaled down from an older technology.
(10) Rule taken from the NCSU CDK.
(11) Value taken from original MOSIS lambda-based rules.
(12) Extension of active area beyond gate appears to be about 100nm in Fig. 10 of [1]. Given the contact size of 65nm, and as small an active enclosure as possible (i.e. 5nm), a 35nm space of contact to gate is implied.
(13) Minimum via overlap value is taken from the 3-sigma overlay value in the 2005 ITRS for the 2007 technology node. This overlap is typically 2 times the overlay value. We have used 3 times this value and inflated it stightly to be conservative and to align to our manufacturing grid. Higher level metals do not have this requirement, so it is only applied to metal1 and the intermediate metal layers.
(14) Anupama Subramaniam from Kevin Cao’s group suggested that field poly spacing should be 1.5 * poly half-pitch for improved yield.
(15) Width/spacing modified to reflect minimum lower metal width, and to be similar to contact rules.
(16) Variable width rules modeled off of GPDK version.
(17) In this case of two tiers integration, Back Metal and VDN are only used for top tier bonding, not for place-and-routing. So they have the dimensions and rules close to Top Metal and VUP, rather than lower layer metals and Vias.

References

[1] H. Nii et. al, “A 45nm High Performance Bulk Logic Platform Technology (CMOS6)using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[2] S. Narasimha et. al., “High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.
[3] E. Josse et. al., “A Cost-Effective Low Power Platform for the 45-nm Technology Node,” IEEE International Electron Devices Meeting (IEDM) Technical Digest, Dec. 11-13 2006.