ECE 720 Place & Route Tutorials
Place & Route Tutorial 1
This tutorial introduces place & route (physical design) with Synopsys IC Compiler at NC State University. It is assumed that you already know how to synthesize standard-cell netlists with Synopsys Design Compiler, following the ECE 520 Tutorials.
Place & Route Tutorial 2
This tutorial introduces clock-tree synthesis and repeater insertion with Synopsys IC Compiler and PrimeTime at NC State University. It also includes the files necessary to run Signal Integrity and Power Estimation using Synopsys PrimeTime-SI, PrimeTime-PX and Mentor Graphics Questa/Modelsim. It is assumed that you have already worked through Place & Route Tutorial #1 and know how to perform the base-line physical design flow.
This tutorial assumes the use of the ARM CORTEXM0 Design Start processor, which we cannot distribute. However, it is relatively simple to swap in any RTL design that you can synthesize and simulate.