Layout Tutorial 2
Layout Tutorial #2: Extraction and LVS
In this tutorial you will create the schematic and layout for a NAND gate, and then perform a layout-vs.-schematic (LVS) check to verify the connectivity. You’ll also perform a parasitic extraction and generate an HSPICE netlist with accurate wire- and source-/drain, adjacent wires capacitances, as well as wire resistances generated from the layout.
Contents
Create the NAND2 Schematic
Create a cell called “nand2”, and make a schematic like the one shown below. Give each transistor three fins. Note that you can add a “Wire Name” to internal nodes by selecting Create->Wire Name or by hitting the “l” (lower case “L”) key. The figure shows that the node between the two NMOS transistors has been given the name “X”. When you generate an HSPICE netlist, this node will now have a more meaningful name, rather than something random like “NET41”.
Check and save the schematic.
Create the NAND2 Layout
Now create the layout view. For the fastest results, start with the completed layout from Layout Tutorial 1. Use the Library Manager to copy the layout cell-view from that cell into this one.
Open the layout and make a few changes. First, we won’t be using the M1A and M1B layers anymore, since they’re not supported for LVS and parasitic extraction. Instead, we will use M1, which is an “uncolored” layer that uses the most dense spacing rules (i.e. M1A-to-M1B spacing rules, rather than M1A-to-M1A spacing rules). Select every M1A and M1B shape and then hit the “q” key to edit it’s properties. Change the layer to M1 and click “Ok”. Note that if you have multiple shapes selected, then you can click the “common” button in the properties dialog to change the layer for multiple shapes at the same time. After changing the shapes, change the via instances by swapping the M1A_AIL2 and M1B_AIL2 vias for M1_AIL2. This can be done in the properties dialog by changing the cell-name. Also swap the M1A_GIL via for M1_GIL. When you are done, assuming you have the “used” checkbox selected in your layer-list, you should see only M1 appear in the layer-list, and M1A and M1B should disappear.
Finally delete the pins “in” and “out”, to be consistent with our new schematic. Create new pins in the M1 layer named “A” and “Z” as shown below. Note that the NW, NIM, and PIM layers are not shown, for clarity.
Now add another finger to each transistor by adding two instances each of nmos_pcell and pmos_pcell to the right of the nmos/pmos_pcell instances that are already there. Change the GATE parameter for these instances from A to B. Then, make sure that the GATEA and GATEB shapes overlap exactly. Finally, paint a small rectangle of GATEA to connect the new dummy shape as shown below. What was previously a dummy GATEB shape is now a new transistor that shares the same active area.
Next, we need to make the M1 connections to match our schematic. Make the following changes. When done, your layout should look like the one below.
- Move the NMOS-drain-connected M1_AIL2 via from the center drain to the right-most drain and create a new M1 rectangle to maintain its connection to the Z output.
- Copy the PMOS-source-connected M1_AIL2 via to the right-most source.
- Copy the M1_GIL via and GIL rectangle from the GATEA line to the opposite side of the GATEB line. Then add a pin in the M1 layers named “B” to this via.
When you are done creating the layout, save the design. Make sure that the layout is DRC clean.
LVS
To perform a layout-vs.-schematic (LVS), choose Calibre->Run LVS…. The LVS form appears, as shown below. If you do not see the window appear, or if you get an error, then it’s possible that you didn’t type “add calibre” as instructed above. You will need to exit Virtoso, log out, and log back in, setting up your environment in the correct order.
There are a number of options you need to set and know what they are.
Rules
Calibre-LVS Rules File and Calibre-LVS Run Directory are already filled in by the tool,leave them as it is.
Inputs
- Select “Hierarchial”, “Layout vs Netlist”
- Under the Layout tab
- Files : nand2.calibre.gds
- Top Cell: nand2
- Layout Netlist: nand2.sp
- These options are already be filled in by the tool, leave them as is
- Format: select “GDSII” and select the option “Export from layout viewer” (This is very important)
- Under the Netlist tab
- Files: nand2.src.net
- Top Cell:nand2
- These options are already be filled in by the tool, leave them as it is
- Format: select “SPICE” and select the option “Export from schematic viewer” (This is very important)
Outputs
- Under the Report/SVDB
- LVS Report File: nand2.lvs.report
- This option is already be filled in by the tool, leave it as is
- svdb directory: svdb
- Select “View Report after LVS Finishes”
Perform an LVS Check without Errors
Set the LVS form with the options shown above. Then click the “Run LVS” button. If LVS runs successfully, with out any error, then you will see the below window with a smile 🙂
Click on the “Transcript” tab in Calibre Interactive – LVS to see the log file.
The LVS Report File – NAND2.lvs.report is also opened and a part of the report is shown below. Note that the netlist was transformed for faster checking, and that the NAND function was recognized in the transformation in both the layout and the schematic (which is called the “source” by Calibre). Note also that the pins were recognized as correspondence points.
CELL COMPARISON RESULTS ( TOP LEVEL )
# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################
LAYOUT CELL NAME: NAND2
SOURCE CELL NAME: NAND2
————————————————————————————————————–
INITIAL NUMBERS OF OBJECTS
————————–
Layout Source Component Type
—— —— ————–
Ports: 5 5
Nets: 6 6
Instances: 2 2 MN (4 pins)
2 2 MP (4 pins)
—— ——
Total Inst: 4 4
NUMBERS OF OBJECTS AFTER TRANSFORMATION
—————————————
Layout Source Component Type
—— —— ————–
Ports: 5 5
Nets: 5 5
Instances: 1 1 _nand2v (5 pins)
—— ——
Total Inst: 1 1
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
——- ——- ——— ——— ———
Ports: 5 5 0 0
Nets: 5 5 0 0
Instances: 1 1 0 0 _nand2v
——- ——- ——— ———
Total Inst: 1 1 0 0
o Initial Correspondence Points:
Ports: A GND! Z B VDD!
Perform an LVS Check with Errors
Just as an example of what can go wrong when running LVS, try removing the M1_AIL2 via that connects the PMOS source node to VDD! in the upper right-hand corner of the layout, as shown below.
Then save the design and re-run the LVS check. You should see the following output.
and the Error report will be as follows
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
LAYOUT CELL NAME: nand2
SOURCE CELL NAME: nand2
————————————————————————————————————–
INITIAL NUMBERS OF OBJECTS
————————–
Layout Source Component Type
—— —— ————–
Ports: 5 5
Nets: 7 6 *
Instances: 2 2 MN (4 pins)
2 2 MP (4 pins)
—— ——
Total Inst: 4 4
NUMBERS OF OBJECTS AFTER TRANSFORMATION
—————————————
Layout Source Component Type
—— —— ————–
Ports: 5 5
Nets: 6 5 *
Instances: 2 0 * MP (4 pins)
0 1 * _nand2v (5 pins)
1 0 * _smn2v (4 pins)
—— ——
Total Inst: 3 1
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
——- ——- ——— ——— ———
Ports: 5 5 0 0
Nets: 5 5 1 0
Instances: 0 0 2 0 MP(PFET)
0 0 0 1 _nand2v
0 0 1 0 _smn2v
——- ——- ——— ———
Total Inst: 0 0 3 1
o Initial Correspondence Points:
Ports: A GND! VDD! Z B
How would you figure out what the problem is from all this information? One thing that you should notice is that the number of nets is listed as 7 in the layout, but only 6 in the schematic (under the INITIAL NUMBERS OF OBJECTS). That means there is an open circuit somewhere. You can double click on the Nets in the RVE and they should be highlighted in the layout. You can also tell the RVE to draw a simple schematic that it has extracted from the layout in the RVE. I use this feature very often when debugging LVS errors. Make sure that everything is connected as you think it should be.
You can also purposefully make a short circuit in either the layout or schematic to see an error. Try making some more errors to get familiar with debugging LVS errors. (IMPORTANT NOTE – whenever you make any change to schematic, make sure you “Check and Save” and not just “Save”, before you run LVS once again. If you dont do so, the LVS will give an error saying it cannot export the schematic.) One aspect that is not currently checked by our LVS rules is the transistor dimensions. Therefore, changing parameters such as NFINS, W, and L in the schematic will not affect the LVS check at all. We hope to fix this in a future release of the FreePDK15.
In general, fixing LVS errors can be hard, so it’s a good idea to add hierarchy to your layout (explained in the next tutorial) and keep things from getting too complex.
Extract Parasitics
Next, fix the layout of the nand2 gate and save the design. Now we’re going to extract the parasitic wire capacitances and resistances from the layout.
To perform a Parasitic Extraction(PEX), choose Calibre->Run PEX…. The PEX form appears, as shown below.
Extract with Parasitic Capacitances and Resistances
There are a number of options you need to set and know what they are. For options not mentioned below, leave them as it is. We will use them in future if required.
Rules
Calibre-LVS Rules File and Calibre-LVS Run Directory are already filled in by the tool,leave them as it is.
Inputs
- Under the Layout tab
- Files : NAND2.calibre.gds
- Top Cell: NAND2
- These options are already be filled in by the tool, leave them as is
- Format: select “GDSII” and select the option “Export from layout viewer” (This is very important)
- Under the Netlist tab
- Files: NAND2.src.net
- Top Cell:NAND2
- These options are already be filled in by the tool, leave them as is
- Format: select “SPICE” and select the option “Export from schematic viewer” (This is very important)
Outputs
- Extraction Type: Select Transistor Level, R + C + CC, No Inductance
- Under the Netlist tab
- File: NAND2.pex.netlist
- This option is already be filled in by the tool, leave it as is
- Format: HSPICE
- Use Names From: SCHEMATIC
- select “View netlist after PEX finishes”
- Under the Nets tab
- Extract parasitics for: Select “All Nets”
- Under the Reports tab
- PEX Report File: NAND2.pex.report
- This option is already be filled in by the tool, leave it as is
- Select “Generate PEX Report” and “View Report after PEX finishes”
- Under the SVDB tab
- SVDB Directory: svdb
Set the PEX form with the options shown above. Then click the “Run PEX” button. If PEX runs sucessfully, with out any error, then you will be able to view PEX Report File – NAND2.pex.report and also PEX Netlist File – NAND2.pex.netlist, which is the extracted netlist from the layout along with parasitic capacitances and resistances.
Click on the “Transcript” tab in Calibre Interactive – PEX to see the log file.
Now let us understand the NAND2.pex.netlist File
The main hspice netlist “NAND2.pex.netlist” contains only the intentionally designed devices.
Filenames with the extensions “.pex” and “.pxi” files are included in the “NAND2.pex.netlist”
- The .pex file (actually called “NAND2.pex.netlist.pex”) contains one subckt per net: each subckt containing the RC tree structure modeling the net.
- The .pxi file (actually called “NAND2.pex.netlist.NAND2.pxi”) contains the connections between the parasitic networks i.e. containing the instance calls to the net model subckts along with the coupling capacitors connecting between these net model instances.
The NAND2.pex.netlist is as shown below
* File: NAND2.pex.netlist
* Created: Sat Jan 30 07:09:41 2016
* Program “Calibre xRC”
* Version “v2013.4_37.29”
*
.include “NAND2.pex.netlist.pex”
.subckt NAND2 A GND! Z B VDD!
*
* VDD! VDD!
* B B
* Z Z
* GND! GND!
* A A
MM0 X N_A_MM0_g N_GND!_MM0_s N_GND!_MM0_b NFET L=2e-08 W=8.8e-08 NFIN=3
+ ADEJ=5.28e-16 ASEJ=4.56e-16 PDEJ=1.32e-07 PSEJ=1.14e-07
MM3 N_Z_MM3_d N_B_MM3_g X N_GND!_MM0_b NFET L=2e-08 W=8.8e-08 NFIN=3
+ ADEJ=9.12e-16 ASEJ=5.28e-16 PDEJ=2.52e-07 PSEJ=1.32e-07
MM1 N_Z_MM1_d N_A_MM0_g N_VDD!_MM1_s N_VDD!_MM1_b PFET L=2e-08 W=8.8e-08 NFIN=3
+ ADEJ=5.28e-16 ASEJ=4.56e-16 PDEJ=1.32e-07 PSEJ=1.14e-07
MM2 N_Z_MM1_d N_B_MM3_g N_VDD!_MM2_s N_VDD!_MM1_b PFET L=2e-08 W=8.8e-08 NFIN=3
+ ADEJ=9.12e-16 ASEJ=5.28e-16 PDEJ=2.52e-07 PSEJ=1.32e-07
c_87 X 0 0.0428739f
*
.include “NAND2.pex.netlist.NAND2.pxi”
*
.ends
*
*
Note also that Calibre has extracted the dimensions of each transistor and the source/drain regions for HSPICE simulation. The L and NFIN parameters are set as we would expect, but the W parameter matches the width of the ACT shape in the layout, not the effective width of the transistor. That’s Ok, because the BSIM-CMG transistor model will ignore the W parameter when the NFIN parameter is present. Also, note that for transistors MM2 & MM3, the areas and perimeters are smaller for the shared source/drain regions than for the non-shared regions. Calibre is calculating these areas according to the shapes in the layout for more accurate HSPICE simulation. You may note these values are also different for MM0 and MM1, but a bug in our LVS rules is currently preventing correct extraction for these values. We anticipate fixing this bug soon.
Extract with Parasitic Capacitances Only
Looking through the .pex and .pxi files, you should see that even this very simple circuit has resulted in hundreds of capacitors and resistors. This level of detail is necessary to achieve the highest degree of accuracy, but for larger circuits, it can slow an HSPICE simulation to a crawl. While the resistances are necessary to accurately understand the delay of a circuit, the power dissipation can be predicted very well using capacitances only. We often call this a “lumped-C model” for a net, as opposed to an “RC-tree model”.
To extract a lumped-C model, make the following change in the Calibre Interactive – PEX window:
Outputs
- Extraction Type: Change from “R + C + CC” to “C + CC”
Re-run PEX, and you should find that you have capacitances only. Not only that, but the number of capacitances has reduced by a factor of 10. Also, the netlist is simpler to read and recognize from your original schematic. Finally, note that the file “NAND2.pex.netlist.pex” is no longer used (or created), because there is no RC tree for each net.
The new, simplified NAND2.pex.netlist is as shown below.
* File: NAND2.pex.netlist
* Created: Sat Jan 30 07:12:14 2016
* Program “Calibre xRC”
* Version “v2013.4_37.29”
*
.subckt NAND2 A GND! Z B VDD!
*
MM0 X A GND! GND! NFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=5.28e-16 ASEJ=4.56e-16
+ PDEJ=1.32e-07 PSEJ=1.14e-07
MM3 Z B X GND! NFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=9.12e-16 ASEJ=5.28e-16
+ PDEJ=2.52e-07 PSEJ=1.32e-07
MM1 Z A VDD! VDD! PFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=5.28e-16 ASEJ=4.56e-16
+ PDEJ=1.32e-07 PSEJ=1.14e-07
MM2 Z B VDD! VDD! PFET L=2e-08 W=8.8e-08 NFIN=3 ADEJ=9.12e-16 ASEJ=5.28e-16
+ PDEJ=2.52e-07 PSEJ=1.32e-07
c_5 A 0 0.0162435f
c_10 GND! 0 0.0761176f
c_16 Z 0 0.0748617f
c_20 B 0 0.0158927f
c_25 VDD! 0 0.112382f
c_28 X 0 0.0442415f
*
.include “NAND2.pex.netlist.NAND2.pxi”
*
.ends
*
*
Congratulations! You have completed the tutorial.
ECE 546Students: Save your final netlist (.pex.netlist, .pex, pxi) and submit using Wolfware. Also submit your LVS results (make sure that the netlists match for full credit).