Layout Tutorial 3

Layout Tutorial 3: Hierarchy

In this tutorial you will create the layout for a hierarchical, sequential circuit, extract it, and simulate it with SPICE.

Create a new cell

Start by creating a cell called “tut3”. Create a new schematic view. The circuit that we will create is shown below. It contains 7 instances of 2 different standard cells from a library called tut3cells. In order to see this library, add the following line to the cds.lib file in the directory where you started Cadence (should be a single line):

DEFINE tut3cells /afs/eos.ncsu.edu/lockers/research/ece/wdavis/tech/ece546/tut3cells_15nm

Next choose View->Refresh in the library manager window. You should see the tut3cells library appear. NOTE: These cells are modified slightly from the NanGate 15nm Open Cell Library.

Create instances

Next, create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the schematic editor window, or press the “I” key. Click Browse and select the tut3cells library. You should see all of the cells in the library. Add 5 instances of “DFFRNQ_X1” “symbol” and 2 instances of “XOR2_X1” “symbol”. Wire the schematic as shown above. Be sure also to add a CLK and RN input pins, and connect it to the flip-flop clocks. Create wire labels with Create -> Wire Name, or press the “L” key. Be sure to follow the instance names (i0 … i6) and net names (n0 … n4) above, to avoid confusion later on in the tutorial. Note that only one schematic pin can be added per net name. The wire-labels for CLK and RN, for example, connect their wires to the CLK and RN pins, even though the wire connection is not drawn.

For your project, it is suggested that you break your design up into units, like these standard-cells, and that you create symbols to refer to these units. In this lab, the symbols are provided for you, but you could have just as easily made them yourself. Start with a completed schematic and choose Design->Create CellView->From CellView… and give the schematic as input.

Next, create a layout view. Create instances of the flip-flop and XOR from the drawing above. Choose Create->Instance in the layout editor window, or press the “I” key. Click “Browse” in the pop-up window and click on the “tut3cells” “DFFRNQ_X1” “layout” cell. Click in the layout to place one instance. Then browse again for the “XOR2_X1” “layout” cell. Add one instance of that as well. Finally, add one instance of the “WELLTAP” “layout” cell. Click “Cancel” to stop adding instances.

Next, zoom out (by pressing “Shift-Z”) and copy the D flip-flop 4 times by selecting Edit->Copy in the layout editor window, or press the “C” key. Click on the instance and click elsewhere to place the copy. Also copy the XOR gate once, and the WELLTAP cell twice. Click “Cancel” or press the Escape key to stop copying instances.

Next arrange the instances so that they appear as in the figure below. Note that the origin is in the lower, left-hand corner. By convention, we usually put the origin in the lower, left-hand corner of our layout. The images below show what you see with (left) and without (right) hierarchy expanded.

Note that the cells in this library are all exactly the same height, have power and ground rails of exactly the same width, and have n-wells with the same Y-dimension. This is necessary to ensure that there are no design-rule violations when tiling them.

Compact the layout

Now, let’s compact the layout so that we use as little area as possible. You’ll notice that the top rail is VDD and the bottom rail is GND for each cell. In order to compact them optimally, we’ll have to flip the cells on row 2. Select each one of these cells and select File->Properties… (or hit “Q”). Under the “attribute” heading, set the “rotation” to “MX”, which stands for “mirrored on the X-axis”. Now compact the layout until it looks like the one below. Note that all layers above ACT have been made invisible to make the NIM & PIM layers easier to see.

Note also the WELLTAP cell. The WELLTAP cell contains N-well and P-well contacts to prevent latchup. Each connected well should have one of these cells, which would mean that we should have at least one per row to get every well. Note that this cell also satisfies the ACT.9 rule, which requires at least one well-contact every 30 um.

DRC check

Next, select Calibre->Run DRC to examine the DRC errors. You will likely have some errors, because it’s difficult to tile the cells correctly. One way to tell if you have tiled the cells correctly is to look at the “prBoundary” shapes (which stands for “Place-and-Route Boundary”). Make sure that the “prBoundary” “drawing” layer is visible in the LSW and make all other layers invisible. (You may need to make this layer valid with Edit->Set Valid Layers… in the LSW before you can set its visibility). When tiled correctly, you should see all of the “prBoundary” shapes touching, with no space between them, as shown below on the left. The one exception is the XOR2_X1 cell in the center of the layout, which must be offset in the X direction in order for the GATEA lines to match the GATEA lines above and below, as shown below on the right.

Note also that the GATEC layer is shown in the image above on the right, along with the GATEA layer. The GATEC layer is a “gate cut” layer, which cuts the gate-metal lines and allows for smaller vertical spacing. Without these gate-cut lines, all transistors that share the same GATEA line would have their gate-nodes shorted together. With the gate-cut, however, gate nodes on opposite sides of the cut are not connected.

Connect supply rails

Next, we need to connect the supply rails so that VDD and GND are each a single net in the extracted view. Connect the power with a metal1 path as shown below and create the labels “vdd!” and “gnd!” for these nets.

Connect signal nets

Next, we need to connect the cells as shown in the schmatic. Look for the labels in the layout view in order to figure out which pin in each standard-cell should be connected to which net in the design.

Connect the layout as shown in the schematic above. While connecting different layers together, you need to use proper vias. The various types of vias available are as follows:

M1_MINT1 : For MINT1 to M1 connection
MINT2_MINT1 : For MINT2 to MINT1 connection
MINT3_MINT2 : For MINT3 to MINT2 connection
MINT4_MINT3 : For MINT4 to MINT3 connection
MINT5_MINT4 : For MINT5 to MINT4 connection
MSMG1_MINT5 : For MSMG1 to MINT5 connection
MSMG2_MSMG1 : For MSMG2 to MSMG1 connection
MSMG3_MSMG2 : For MSMG3 to MSMG2 connection
MSMG4_MSMG3 : For MSMG4 to MSMG3 connection
MSMG5_MSMG4 : For MSMG5 to MSMG4 connection
MG1_MSMG5 : For MG1 to MSMG5 connection
MG2_MG1 : For MG2 to MG1 connection

As you should notice, the vias are available for connecting one metal layer to the next higher layer. So if you need to connect MINT1 to MINT3 then you need to place both MINT2_MINT1 and MINT3_MINT2 contacts together.

You should be very careful while placing contacts. Incorrect contacts can short two nets and result in an LVS Error.

Create pins for all of the inputs and outputs (A<0>, A<1>, A<2>, B<0>, B<1>). Be sure also to add a clock node (called CLK) and reset node (called RN) and connect all of their related input pins on the DFFRNQ_X1 cells. Do NOT create labels for the interior nodes (n0, … , n4). Doing so would cause these nodes to be interpreted as ports by Calibre, causing you to fail the LVS check. When you are done, the layout should look like the one below. Notice that this figure shows only M1, MINT1, and MINT2, but you’re free to use as many (or as few) layers as you wish.

LVS check

Perform an LVS check to make sure that your layout matches your schematic. You may find that you had a number of errors that you need to fix. This process becomes increasingly difficult as the layout gets larger. What’s more, if you don’t trust the layout of the standard-cells to be correct, then this process is nearly impossible. Therefore, it is strongly suggested that you use hierarchy as your layout increases in complexity, performing LVS checks at each level to make sure that everything is correct.

Layout extraction

Now extract the parasitics with Calibre and create an HSPICE netlist. Use the “C+CC” option to keep the netlist small.

Open the netlist you just created. You should notice that it includes all capacitances and that it contains one top-level subcircuit definition, named TUT3.

Verification Simulation

Create a new file called tut3_sim.sp. Set it up to perform a transient simulation that lasts 500ps. Next, assuming that you named your layout cell TUT3, include the file TUT3.pex.netlist and create an instance of the top-level subcircuit in that file. You’ll need to follow the port-order in your particular TUT3.pex.netlist file, but in my case, the lines I add look like this:

.include ‘TUT3.pex.netlist’
X0 CLK RN VDD! A<0> A<1> A<2> B<0> B<1> GND! TUT3

Note that the name of the cell (TUT3) appears at the beginning of the .SUBCKT statement in TUT3.pex.netlist, but appears at the end of the instance statement above.

Next, add the following sources:

Vclk CLK 0 PULSE 0 0.8 0 3p 3p 22p 50p
Vdd VDD! 0 0.8
Vrn RN 0 0.8

The first is a clock source, with a 50ps period and 3ps rise and fall times. The second is the supply voltage. The third ensures that the flip-flops are never reset. The only thing that remains is input patterns for A<0>, A<1>, and A<2>. To implement these signals, add the following line…

.VEC ’tut3.dat’

…and then create a text file called tut3.dat in the directory where you will run HSPICE. Cut-and-paste the contents of the box below to put into this file. You’ll notice from the comments below that this file defines input patterns for all of your signals in a very convenient format.

; Digital input pattern for HSPICE
; “;” is a flag for comments line
;
; To use this digital input pattern, in your Hspice netlist,
; add one line: .VEC ‘vectors.dat’
; Don’t connect any voltage source to the pin/terminal which
; you want to feed with this digital stream.
;
; This file can be used for any system-level simulation.
; Just modify the patterns below.
;
; For more information, see the section title “Specifying
; a Digital Vector File” in the HSPICE Simulation and
; Analysis User Guide (linked from the HSPICE “documentation
; page” link on the course web-page, under “tool tips”)

;
; Define the radix for each pin (1 for each pin)
radix 1 1 1
; List the pin names
vname A<0> A<1> A<2>
; Define pin I/O (i for each pin)
io    i i i
; Define time unit (ns in this example)
tunit ns
; Define slope of signal edge (3 ps rising/falling
; time in this example)
slope 0.003
; Define high voltage (0.8V)
vih   0.8
; Define low voltage (0V)
vil   0.0
; Define the delay for the first instruction
; (10 ps in this example, to shift away from the clock edge)
tdelay 0.01
; Define the period for the vectors (50 ps in this example)
period 0.05
;
; The following are the vectors
; A<0> A<1> A<2>
;
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1

Run the HSPICE simulation. You should see waveforms like the ones below.

Critical Path Simulation

The waveforms above demonstrate the circuit’s functionality, but they do not necessarily demonstrate the critical-path delay. We need a set of vectors that demonstrates the critical-path so that we can measure its delay in HSPICE. In addition, we’d like to use “R + C + CC” extraction, so that we get the best idea of the delay introduced by the wire resistances.

Unfortunately, setting up this critical-path simulation can be difficult, because the netlists can get very large, complex, and slow to simulate. We can simplify things by recognizing that we don’t need to include every node in the simulation. All we need are the nodes in the critical-path, which most-likely includes the nodes n0 or n1, n3, and n4, plus the flip-flops and XOR gates connected to those nodes. We’ll also need to have nodes A<0>, A<1>, and CLK so that we can properly drive the flip-flops, and node B<1> so that we can properly check if it’s working. For the other nodes (such as n2), we’ll need to sensitize the path, which means that we need to choose some constant value that allows node n4 to change whenever n3 changes. But we don’t need parasitic information for n2.

To extract parasitics for the nodes of interest, return to the Calibre Interactive – PEX window, and change the options as follows:

Under Inputs -> Layout, deselect Export from layout viewer. Assuming that you already have already run PEX once, the gds file in the directory should be up-to-date and doesn’t need to be exported again.
Likewise, deselect Export from schematic viewer under Inputs -> Netlist
Under Outputs, change the extraction type to R + C + CC
Under Outputs -> Nets, select Extract parasitics for: Specified Nets. The click the Top-Level Nets tab, select Include and enter the following net names in the box to the right (all on one line):

A<0> A<1> CLK n0 n1 n3 n4 B<1>
Xi0/CLKN Xi0/CLK2 Xi0/n1 Xi0/n2 Xi0/n3 Xi0/n4 Xi0/n5 Xi0/n6 Xi0/n7 Xi0/n8 Xi0/n9
Xi1/CLKN Xi1/CLK2 Xi1/n1 Xi1/n2 Xi1/n3 Xi1/n4 Xi1/n5 Xi1/n6 Xi1/n7 Xi1/n8 Xi1/n9
Xi4/CLKN Xi4/CLK2 Xi4/n1 Xi4/n2 Xi4/n3 Xi4/n4 Xi4/n5 Xi4/n6 Xi4/n7 Xi4/n8 Xi4/n9
Xi5/n0 Xi5/n1 Xi5/n2 Xi5/n3
Xi6/n0 Xi6/n1 Xi6/n2 Xi6/n3

Note that the top line above includes the top-level net names of interest. The next three lines give the internal names of the three flip-flops of interest, and the last two lines give the internal names of the XOR gates. The slash “/” is used to denote levels of hierarchy, and all internal names have the prefix “X”, which follows the HSPICE naming scheme for subcircuit instances. If you get tired of cutting and pasting into the Calibre Interactive window, note that you can edit the line pexPexTopLevelIncludeNetsValue in the file .runset.calibre.pex to include the nets you want. You can then load this file with the command File -> Load Runset. Be sure to say “no” when asked if you want to save the runset, or it will overwrite the changes you just made.

If you’re worried that the names you enetered may not have been recognized by Calibre, you can look for the following lines in the PEX transcript:

— CREATING XREF INFORMATION FROM XDB DATABASE

Selected nets:
A<0> will be included.
A<1> will be included.
…

If Calibre did not recognize one or more of the net names you specified, you will see error messages here.

One more optimization remains. When simulating large systems, it can be very inconvenient to deal with the huge amount of data that is produced. Your disk-quota can fill up very quickly, and simulations can be slowed by the amount of time needed to physically write all of the output data to disk. You can speed this up by telling HSPICE to include only the nodes of interest in the output. Do this by specifying the option PROBE before the POST option in your .OPTION statement, and then adding a .PROBE statement to list the variables that you want in your output file:

.OPTIONS …
+ PROBE POST
.PROBE TRAN v(a<0>) v(a<1>) v(a<2>) v(b<0>) v(b<1>) v(clk)

Note that if you want to see the internal nodes to the subcircuit X0, then you’ll need to include it in the list above as “X0.nodename“. The nodes will have changed names due to the parasitic extraction process, and your node names may differ from mine. But in my case, the node n4 has been mapped to 5 different nodes in the extracted netlist, one of which is named “N_N4_XI4.MM0_g”. Look in your own TUT3.pex.netlist file to find out how your node names have been mapped. So, if I wanted to include this internal node in my .PROBE list, I would write it as

.PROBE TRAN v(X0.N_N4_XI4.MM0_g)

Make these changes now to simulate the critical-path of this design. Suggest a set of vectors that sensitize the critical-path and measure its delay. Assume that the critical-path starts at node CLK(meaning that it will include the CLK-Q delay) and ends at node n4. Be sure to include a mix of rising and falling transitions to verify that you’re actually measuring the longest delay.

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